The 555 timer in practice: astable, monostable and the traps

The 555 has been in production since 1972 and is still made by the hundreds of millions a year, which is odd for a chip that a microcontroller can imitate for the same money. It survives because it does one thing with nothing to program, on any supply from 5 to 15 V, with enough output to drive a relay, and because an engineer who understands the three-resistor divider inside it can predict exactly what it will do. This guide is that understanding: the circuit inside, the two ways it is wired, the parts that keep it honest, and the mistakes that everyone makes once.

What is inside: two comparators, a flip-flop and a discharge transistor

Three equal resistors in series across the supply divide it into thirds. Comparator 1 watches the threshold pin (6) against the upper tap at ⅔ Vcc; comparator 2 watches the trigger pin (2) against the lower tap at ⅓ Vcc. The two comparators set and reset a flip-flop; the flip-flop drives a push-pull output stage on pin 3 and, in the opposite sense, a transistor whose open collector is the discharge pin (7). A reset pin (4) overrides the flip-flop when pulled low, and the control pin (5) is the ⅔ Vcc tap brought outside so that it can be decoupled or deliberately moved.

That is the whole device. Pull pin 2 below ⅓ Vcc and the flip-flop sets: output high, discharge transistor off. Let pin 6 rise above ⅔ Vcc and it resets: output low, discharge transistor on. Every 555 circuit is a way of making a capacitor cross those two levels, and the timing always comes out as a resistance times a capacitance times a logarithm: ln 2 = 0.693 for a swing between the two taps, ln 3 = 1.099 for a charge from zero to the upper one. Hans Camenzind designed it for Signetics in 1971 as a general-purpose timer; he has said the number was the marketing department's choice and not a reference to the three 5 kΩ resistors, though the coincidence is a good way to remember what is inside.

Astable: the RC charges up, then down

Wire R1 from Vcc to pin 7, R2 from pin 7 to pins 6 and 2 joined, and C from there to ground, and the chip oscillates. With the discharge transistor off, C charges from Vcc through R1 + R2; when it reaches ⅔ Vcc the flip-flop resets, the output goes low and pin 7 pulls the junction of R1 and R2 to ground. C now discharges through R2 alone into pin 7, and when it falls to ⅓ Vcc the trigger comparator sets the flip-flop again, the output goes high, pin 7 lets go, and C charges again. The capacitor never sees the top or the bottom of the supply; it sawtooths between the two taps, and the output is a rectangle that is high while it charges and low while it discharges.

A capacitor charging towards a target from one third to two thirds of the way covers exactly half of the remaining distance, which takes RC ln 2, and discharging from two thirds to one third is the same half, so the two times are:

The asymmetry is built in. Charging goes through both resistors and discharging through only one, so t_high is always longer than t_low and the duty cycle is always above 50 %. Making R1 tiny pushes it towards 50 % but not below, and R1 cannot be zero because pin 7 would then short the supply during every low period. For a genuine sub-50 % duty a diode from pin 7 to pins 6 and 2 lets the capacitor charge through R1 alone, bypassing R2, so that R1 sets the high time and R2 the low time independently; the price is that the diode drop subtracts from the charging voltage and the high time then depends a little on the supply. The datasheets write the frequency with 1.44 in the numerator, which is 1 ÷ ln 2 rounded; the 555 timer calculator keeps 0.693 throughout so that the high time, the low time and the period agree exactly.

Monostable: one clean pulse per trigger

Wire R from Vcc to pins 6 and 7 joined, C from there to ground, and hold pin 2 high through a pull-up. At rest the flip-flop is reset: the output is low and the discharge transistor holds C at zero. A pulse taking pin 2 below ⅓ Vcc sets the flip-flop, the output goes high, the discharge transistor releases C, and C charges from zero through R. When it reaches ⅔ Vcc the flip-flop resets, the output drops and C is discharged again, ready for the next trigger. Charging from zero to two thirds of the way takes RC ln 3:

Two rules come with it. The trigger must be a pulse shorter than T: the trigger comparator has priority inside the chip, so while pin 2 is held low the output stays high whatever the capacitor does, and a switch held down for longer than the delay simply stretches it. If the trigger source is slow, a small capacitor and pull-up in front of pin 2 turn its falling edge into a short pulse. And the standard 555 monostable is not retriggerable: a second trigger during the pulse finds the flip-flop already set and does nothing, so the pulse ends 1.1 RC after the first trigger, not the last. A retriggerable version needs an external transistor across C to empty it on each trigger, which is exactly the classic missing-pulse detector, or a different part (the 74HC123 is retriggerable by design). Pin 4 taken low ends the pulse early and discharges C, which makes a clean external cancel.

Choosing the parts

The chip contributes about 1 % to the timing error and the resistors, if metal film, about the same. The capacitor contributes the rest, so it deserves the most thought. For anything below about 100 nF use a C0G/NP0 ceramic: ±5 % or better, no change with voltage, negligible drift with temperature and age. From 10 nF to a few microfarads use a polyester or polypropylene film capacitor: ±5–10 %, stable, low leakage. Avoid X7R and especially Y5V class 2 ceramics for timing: an X7R loses 10–30 % of its capacitance with DC bias and drifts ±15 % over temperature, and a Y5V can halve when warm. Reserve aluminium electrolytics for delays of seconds and longer where ±20 % or worse is acceptable, and check the leakage: a 100 µF electrolytic can leak several microamps, which is a large fraction of the charging current through a 1 MΩ resistor at 5 V, and the capacitor then approaches ⅔ Vcc slowly or never. A tantalum or a low-leakage aluminium part helps; so does a smaller resistor and a smaller, better capacitor.

Resistors: metal film, 1 %, between about 1 kΩ and 1 MΩ. The lower limit is the discharge transistor, which has to pull the bottom of R1 to ground against the supply for the whole low period and whose saturation voltage begins to distort the timing when the current is more than a few milliamps. The upper limit on a bipolar part is the input current of the threshold pin, up to 0.25 µA, which is 2.5 % of the current through 10 MΩ at 5 V; a CMOS part draws picoamps and tolerates far higher values. Between 1 nF and 100 µF for C and 1 kΩ and 1 MΩ for R the formula is trustworthy, and a design that needs values outside that box is usually better done by changing the ratio of R to C.

Bipolar or CMOS

The original bipolar NE555 (also SA555, LM555, and the dual NE556) runs from 4.5 to 16 V, draws 3–6 mA quiescent at 5 V and up to 15 mA at 15 V, and its output can source or sink 200 mA, though the high level is about 1.7 V below Vcc. Its vice is the supply: the push-pull output conducts briefly from rail to rail on every transition, a current spike of the order of 100 mA lasting tens of nanoseconds, which without decoupling drops the supply enough to upset the comparators (the 555 can even retrigger itself) and anything else on the same rail. A 100 nF ceramic at pin 8 and a 10–100 µF electrolytic nearby are not optional.

The CMOS versions (TLC555 and LMC555 from Texas Instruments, the ICM7555 and its "7555" descendants) run from 2 to 15 V, draw tens to hundreds of microamps, swing their output almost rail to rail, have no supply spike, and oscillate to 1–2 MHz against the bipolar part's 100 kHz. Their thresholds sit at precisely ⅓ and ⅔ Vcc, so the timing follows the formula a little more closely. What they lack is drive: the TLC555 sinks 100 mA but sources only about 10 mA, and they are ordinary CMOS in their sensitivity to static and to inputs taken outside the rails. Choose CMOS for battery equipment, for high frequency, for large timing resistors and for anything sharing a supply with a microcontroller; choose bipolar where 200 mA of drive on a rough 12 V supply is the point.

Traps that cost an afternoon

• Pin 5 left floating. The ⅔ Vcc tap is a 5 kΩ-ish node hanging in the air; noise on it moves both thresholds and jitters the timing. Always 10 nF from pin 5 to ground.
• No decoupling on a bipolar part. The transition spike resets the microcontroller next to it, or the 555 itself, or puts a click in the audio. 100 nF at the pin plus bulk capacitance.
• Reset left floating. Pin 4 below about 0.7 V holds the output low. Unconnected, it picks up whatever is nearby; on a CMOS part it must be tied. Connect it to Vcc, or drive it deliberately.
• An inductive load with no diode. A relay coil or a small motor on pin 3 kicks back tens of volts at turn-off and the output stage does not survive many of them. A diode across the coil, cathode to the positive side.
• Expecting better than 5 %. With an electrolytic timing capacitor the circuit is a ±20 % device, and no trimmer fixes the temperature drift. If the number matters, use a film capacitor and a trimmer, or a crystal and a counter.
• Running a bipolar part above 100 kHz. The output rise and fall times and the comparator delays are fixed nanoseconds that become a large fraction of a short period; the frequency falls short of the formula and the waveform degrades. CMOS to 1 MHz, and something else beyond.
• Frequency that moves with the supply. The formula has no Vcc in it, but a bipolar part's thresholds are not exactly at the taps and the discharge transistor's saturation depends on current, so a 12 V rail that sags to 10 V under load shifts the timing by a fraction of a per cent per volt, visible on a long delay. Regulate the supply or use a CMOS part, whose thresholds track the rail exactly.
• R1 too small. Below 1 kΩ, pin 7 sinks more than Vcc ÷ 1 kΩ every low period; the chip warms and the low time stretches. Scale C up and the resistors with it.

Where a 555 still beats a microcontroller

Where there is no firmware and never will be. A delay-on relay in a control panel that must give a compressor two minutes between starts: a monostable with R = 1 MΩ and C = 100 µF and a 200 mA output driving the relay directly, on the panel's 12 or 24 V control supply, with nothing to program, no boot time and nothing for a technician to misunderstand. A PWM source for a small fan or a DC motor: an astable with the diode across R2 and a potentiometer in place of the two resistors gives a duty that sweeps from a few per cent to nearly 100 at a fixed frequency, driving a logic-level MOSFET. A flasher or beacon that runs from any battery. A missing-pulse detector on a machine: a monostable retriggered by every pulse from a sensor on a shaft, with a transistor emptying C on each trigger, whose output drops the moment a pulse fails to arrive, which is the same circuit as a hardware watchdog for a controller that has crashed. In each case the 555 is doing a job whose timing tolerance is loose and whose failure mode must be simple and visible.

Where it does not win: anything that needs better than a few per cent, several timings, communication, temperature compensation, a frequency above 100 kHz, or the lowest current on a battery. Those belong in a microcontroller, whose timers are crystal-accurate and whose cost is now the same as the chip they replace. In Ahmedonics' own boards the 555 turns up as a watchdog or as a delay-on for a contactor beside a microcontroller that does the real work, which is a fair description of its place in modern design: not the brain, but the part of the circuit that must work when the brain does not.

The example in numbers

The astable with R1 = 10 kΩ, R2 = 47 kΩ and C = 100 nF on 5 V:

1. R1 + 2R2 = 104 kΩ; f = 1 ÷ (0.693 × 104 000 × 100 × 10⁻⁹) = 138.8 Hz (138.5 Hz with the datasheet's 1.44).
2. t_high = 0.693 × 57 kΩ × 100 nF = 3.95 ms; t_low = 0.693 × 47 kΩ × 100 nF = 3.26 ms; period 7.21 ms; duty 57 ÷ 104 = 54.8 %.
3. The capacitor sawtooths between 1.67 and 3.33 V; while the output is low, pin 7 sinks 5 V ÷ 10 kΩ = 0.5 mA through R1.

Designing the other way, for 1 kHz at 60 % with the same 100 nF: R1 + 2R2 must be 1 ÷ (0.693 × 1 000 × 100 × 10⁻⁹) = 14.43 kΩ, so R1 = 0.2 × 14.43 = 2.89 kΩ and R2 = 0.4 × 14.43 = 5.77 kΩ; with the nearest E24 values, 3 kΩ and 5.6 kΩ, the circuit runs at 1 016 Hz and 60.6 %. A monostable with R = 100 kΩ and C = 10 µF gives a pulse of 1.0986 × 1 s = 1.10 s, and with a ±20 % electrolytic anything from 0.9 to 1.3 s. The calculator reproduces all three and flags the resistor, capacitor, frequency and supply limits described above.

References

• Texas Instruments, xx555 Precision Timers (NE555, SA555, SE555) datasheet — supply range, supply current, output drive, thresholds, timing accuracy and the application circuits
• Texas Instruments, TLC555 LinCMOS Timer datasheet — the CMOS part: 2–15 V, supply current, 2 MHz, output sink and source ratings
• H. Camenzind, Designing Analog Chips, 2005 — the 555 described by its designer, with its internal circuit
• P. Horowitz and W. Hill, The Art of Electronics, 3rd ed., Cambridge University Press, 2015 — §7.1.3, the 555 and its relatives; §1.4, RC charging and the time constant
• IEC 60063:2015, Preferred number series for resistors and capacitors — E12, E24 and E96 values