PCB Trace Width Calculator — IPC-2221, Resistance & Drop

What the calculator does

A copper trace is a resistor, and a current through it makes heat that has to leave through the board and the air. The trace gets wider until the temperature rise is acceptable; that is the whole design problem, and IPC-2221 reduces it to a curve fit relating current, temperature rise and copper cross-section. The calculator solves that fit for the cross-section, divides by the copper thickness for the width, and does it for the other layer type too, because a trace buried inside the board has no air to cool it and needs about twice the width.

It then treats the trace as the resistor it is: resistance over its length at the temperature it will run at, the voltage lost along it and the power turned into heat. And if you already have a width in mind, from a footprint, a via pitch or the board you are looking at, it tells you what that width carries at the allowed rise and how hot it would run at your current.

Formula

IPC-2221 I = k × ΔT^0.44 × A^0.725 (I in A, ΔT in °C, A in mil²)
Cross-section A = (I ÷ (k × ΔT^0.44))^{1 ÷ 0.725} k = 0.048 external, 0.024 internal
Thickness t = 1.378 mil × oz Width w = A ÷ t 1 mil = 0.0254 mm

Resistance R = ρ × L ÷ (w × t) ρ_Cu = 1.72 × 10⁻⁸ Ω·m × (1 + 0.00393 × (T − 20 °C)) T = T_ambient + ΔT
Drop V = I × R Loss P = I² × R

For a given width: I = k × ΔT^0.44 × A^0.725 ΔT = (I ÷ (k × A^0.725))^{1 ÷ 0.44}

The exponents and the two values of k are the closed-form fit to the IPC-2221 charts (section 6.2 of IPC-2221B), which are themselves the 1950s National Bureau of Standards measurements on traces alone on a board in still air. The area is in square mils because the fit was made in mils; the calculator converts. One ounce of copper per square foot is 35 µm (1.378 mil) thick, so 1 oz, 2 oz and 3 oz copper are 35, 70 and 105 µm, and half-ounce is 17.5 µm.

Worked example

A 3 A supply trace on an outer layer of a 1 oz board for a motor driver: 10 °C rise allowed, 50 mm long, the board at 25 °C, and a 1.0 mm width already drawn because that is what fits between two connector pins.

10^0.44 = 2.754, so k × ΔT^0.44 = 0.048 × 2.754 = 0.1322 on an external layer.
A = (3 ÷ 0.1322)^1.3793 = 22.69^1.3793 = 74.2 mil² (0.0478 mm²).
Width = 74.2 ÷ 1.378 mil = 53.8 mil = 1.37 mm. On an internal layer k is 0.024, the area is 193 mil² and the width 3.56 mm.
Resistance of the 1.37 mm × 35 µm trace over 50 mm at 25 + 10 = 35 °C: ρ = 1.72 × 10⁻⁸ × 1.059 = 1.82 × 10⁻⁸ Ω·m; R = 1.82 × 10⁻⁸ × 0.05 ÷ (1.37 × 10⁻³ × 35 × 10⁻⁶) = 19.0 mΩ. Drop 3 × 0.019 = 57 mV; loss 3² × 0.019 = 0.171 W.
The 1.0 mm trace you drew: A = 39.37 mil × 1.378 mil = 54.3 mil². At a 10 °C rise it carries 0.1322 × 54.3^0.725 = 2.39 A; at 3 A its rise is (3 ÷ (0.048 × 54.3^0.725))^2.273 = 16.7 °C; at that temperature it is 26.7 mΩ over the 50 mm, drops 80 mV and dissipates 0.240 W.

So 1.0 mm is 73 % of what 3 A needs at 10 °C. It will not fail: 17 °C above a 25 °C board is a 42 °C trace, well below what FR-4 tolerates. But the same trace in a sealed enclosure at 55 °C in a Faisalabad summer, with the driver heating the board too, starts from a much higher baseline, and the 0.24 W it dissipates is 0.24 W the enclosure has to shed. Widen it to 1.4 mm, or move the pins.

Required trace widths at a 10 °C rise

Current	1 oz external	2 oz external	1 oz internal
1 A	0.30 mm (11.8 mil)	0.15 mm (5.9 mil)	0.78 mm (30.8 mil)
2 A	0.78 mm (30.8 mil)	0.39 mm (15.4 mil)	2.03 mm (80.0 mil)
3 A	1.37 mm (53.8 mil)	0.68 mm (26.9 mil)	3.56 mm (140.0 mil)
5 A	2.77 mm (108.9 mil)	1.38 mm (54.4 mil)	7.19 mm (283.2 mil)
10 A	7.19 mm (283.2 mil)	3.60 mm (141.6 mil)	18.7 mm (736.8 mil)
20 A	18.7 mm (736.8 mil)	9.36 mm (368.4 mil)	48.7 mm (1 917 mil)

IPC-2221 external k = 0.048, internal k = 0.024, 10 °C rise. The chart runs to about 35 A and 400 mil (10 mm); the 20 A row on 1 oz copper and the internal rows at 10 A and above are extrapolations, and at those currents a plane or several layers in parallel is the real answer. Halving k is the same as doubling the current: an internal trace needs the area an external trace would need for twice the current.

Assumptions and limitations

IPC-2221 is a conservative fit to old data. The curves come from measurements made in the 1950s on a single trace on a bare board in still air, and they have been carried through MIL-STD-275, IPC-D-275 and IPC-2221 since. They do not know about the board's thickness, the copper planes beside and beneath the trace, an enclosure or the altitude.
IPC-2152 (2009) is the modern standard. It measured real boards and found that the laminate and nearby planes carry away far more heat than the old charts assumed, so a trace on a board with planes can be narrower for the same rise, while a trace in a sealed enclosure, or at altitude where the air is thinner, must be wider. It also found little difference between internal and external traces on such boards. For a power design, use IPC-2152's charts or a thermal simulation; use this calculator for the first pass and for boards without planes.
Vias are not traces. A 0.3 mm via with 25 µm of plating has a copper cross-section of about 24 000 µm² (37 mil²), which the same fit puts at 1.8 A external and 0.9 A internal at 10 °C; as a rule of thumb, count about 1 A per such via and use several in parallel for a power connection, with IPC-6012 setting the minimum plating.
The connector or terminal usually limits first. A 2.54 mm header pin is rated 1–3 A, a 5.08 mm screw terminal 10–16 A, a JST-XH contact 3 A. Check the mating parts before widening the copper.
Thermal relief, solder mask and pours. A thermal-relief connection to a plane is four thin spokes, each a narrow trace; a pad on a 10 A plane must be connected solidly or through wide spokes. Solder mask makes a small difference to cooling and is ignored. A copper pour beside a trace helps it, which is one reason the old charts are conservative.
Outer layers are thicker than their foil. On a board with plated holes, the outer layers receive 20–35 µm of plated copper on top of the foil, so "1 oz" outer copper is often 50–70 µm finished. The calculator uses the nominal foil thickness, which is on the safe side; inner layers are the foil only. Etching also narrows a trace slightly at its base.
DC only. At high frequency the current crowds into the surface of the copper (the skin depth in copper is 66 µm at 1 MHz and 2 µm at 1 GHz), and the resistance rises; the calculator is for DC and 50 Hz.
Fusing is a different calculation. The current that melts a trace in a short time, for a fault or a pulse, is given by the Onderdonk equation (and the Preece equation for the steady state); it is not done here. A trace sized for a 10 °C rise is a long way below its fusing current.

Frequently asked questions

Why does an internal trace need twice the width?

In the IPC-2221 model an external trace sheds heat to the air above it by convection and radiation as well as into the board; an internal trace can only conduct into the laminate, which is a poor conductor, and the charts halve k to allow for it. The factor is a pessimistic legacy: IPC-2152's measurements on real multilayer boards, where planes spread the heat, found internal traces run about as cool as external ones. Keep the factor for a board with no planes; for a four-layer board with ground and power planes the truth is in between and usually closer to the external figure.

Is a 10 °C rise the right target?

It is the conventional conservative value and a sensible default for anything in an enclosure, near components that are already hot, or on a board whose ambient is uncertain. FR-4 laminate is good to 130 °C or more (its glass transition temperature), and copper does not care, so a 20–30 °C rise is common on power boards with airflow and known ambients. What the rise costs is the board's temperature budget: a 30 °C rise on a trace next to an electrolytic capacitor at 60 °C ambient shortens that capacitor's life, and the trace's resistance climbs 0.4 % for every degree.

Is 2 oz copper worth the cost?

It halves the width for the same current and halves the resistance for the same width, and on a small board where 10 A has to pass between fine-pitch parts it is often the only way. The costs are real: a higher board price, a minimum trace width and spacing that roughly doubles (thicker copper cannot be etched as finely), and more heat needed to solder large pads. Most designs are better served by 1 oz copper with wider traces, pours on both sides stitched with vias, and 2 oz reserved for boards that are genuinely about current.

How wide for 20 A?

The table says 18.7 mm on 1 oz external copper, which is beyond the chart and impractical as a trace. At 20 A the design changes: a copper pour or plane on two or more layers stitched with a field of vias, 2 oz copper, a bus bar soldered to the board, or a connector and a cable that bypass the board altogether. IPC-2152 covers planes; for a plane the width is the whole board and the limit becomes the connector, the via field and the terminal.

Can I thicken a trace with solder?

Roughly, yes. A trace left free of solder mask and flooded with solder gains a bead of tin-lead or SAC alloy whose resistivity is about eight times that of copper, so a 0.5 mm bead on a 35 µm trace adds the equivalent of about 60 µm of copper, roughly doubling or tripling the capacity. It is uneven, depends on the operator, makes the board unrepairable if it wicks, and is not accepted in a production design under IPC-A-610; it is a legitimate rescue on a prototype, and a signal that the next revision needs wider copper.

Do I need to worry about the voltage drop along a trace?

For a power trace, rarely: 57 mV on a 12 V rail is nothing. For three cases, always. A current-sense resistor of 10 mΩ read by traces that also carry the current will read the trace resistance too, so its sense lines must connect at the resistor's pads in a Kelvin (four-wire) pattern. A long thin ground return under an ADC reference or a sensor shifts the measurement by the drop. And an LED string or a heater fed through 19 mΩ of copper loses less than the connector does, but a 5 V, 3 A LED strip on 200 mm of 0.5 mm trace loses 0.3 V and is visibly dimmer at the far end.

References

IPC-2221B, Generic Standard on Printed Board Design, section 6.2 (conductor thickness and width for internal and external layers) — the charts and their curve fit used here
IPC-2152, Standard for Determining Current-Carrying Capacity in Printed Board Design, 2009 — measured data on real boards: planes, board thickness, enclosures and altitude
IPC-6012, Qualification and Performance Specification for Rigid Printed Boards — minimum copper plating in holes and on surfaces
Douglas Brooks and Johannes Adam, PCB Design Guide to Via and Trace Currents and Temperatures, Artech House, 2021 — the physics behind the charts, thermal simulation and via currents
IPC-A-610, Acceptability of Electronic Assemblies — what a production assembly may and may not look like, including solder on conductors

Last reviewed 2026-09-20.

PCB trace width calculator (IPC-2221)

Trace width